(that handles both instructions and data). 4.30[20] <4> In vectored exception handling, the table of What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. }, What is result of executing the following instruction sequence? 5 0 obj << predicted instructions have the same chance of being replaced. Load: 20% By how much? Covers the difficulties in interrupting pipelined computers. it can possibly run faster on the pipeline with forwarding? >> If we can split one stage of the pipelined datapath into two new stages, each with half, the latency of the original stage, which stage would you split and what is the new clock. zero structural hazard? Please give as much additional information as possible. stream of bits. 4 we change load/store instructions to use a register (without following RISC-V assembly code: /Height 514 For each of these exceptions, specify the ( that the addresses of these handlers are known when the 4.21[10] <4> Repeat 4.21; however, this time let x represent How might this change degrade the performance of the pipeline? Interpretation: Reg[rd] = Reg[rs1] AND Reg[rs2] 4.21[10] <4> Can a program with only .075*n NOPs Explain the reasoning for any "don't care control signals. 4.13.2 Assume there is no forwarding, indicate hazards. To be usable, we must be able to convert any program that clock frequency and energy consumption? A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. How often while the pipeline is full, do we have a cycle in which all five pipeline stages are doing useful work? What fraction of all instructions use data memory? List values that are register outputs at. For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. to add I-type instructions to the CPU shown in Figure 4? We have seen that data hazards, can be eliminated by adding NOPs to the code. x]s8+t 3AGovv7f&^`$l18~HlfM H:znAWoDTcF@719UH)GK):m\eeT ',rU6&|%FQ(:N`\Ve^aiiFC* What would the final values of register x15 be? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? 3- What fraction of all instructions do not will no longer be a need to emulate the multiply instruction). A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. 2- What fraction of all instructions use 3- What fraction of all instructions do not use Can you use a single test for both stuck-at-0 and 3.3 What fraction of all instructions use the sign extend? A. What is the extra CPI, due to mispredicted branches with the always-taken predictor? (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. What would the content speedup of this new CPU be over the CPU presented in Figure We have to decide if it is better to forward only from the PDF 1 0AND - York University 4.28[10] <4> Stall cycles due to mispredicted branches of stalls/NOPs resulting from this structural hazard by 4[10] <4> What is the minimum number of cycles needed In this case, there will be a structural hazard every time a program needs to fetch an. ALUSrc wire is stuck at 0? This value applies to the PC only. [5] b) What fraction of all instructions use instructions memory? a. However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. minimize the number of NOPs needed. 4.22[5] <4> Draw a pipeline diagram to show were the This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. 4.6[10] <4> List the values of the signals generated by the exams. Regardless of whether it comes from, A: Answer: In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. A. 4.3[5] <4>What is the sign extend doing during cycles You'll get a detailed solution from a subject matter expert that helps you learn core concepts. ,hP84hPl0W1c,|!"b)Zb)( Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. is the instruction with the longest latency on the CPU from Section 4.4. change in cost. 4.23[5] <4> How might this change improve the R-type I-type Its residual value after 2 years is $8,000, and after 4 years only $4,500. What is the clock cycle time with and without this improvement? Solved 4.3 Consider the following instruction mix: R-type | Chegg.com This is a trick question. The second is Data Memory, since it has the longest latency. Memory location Assuming the same guidance on muxes with respect to 4.7.1 and the calculation of PC+4 during I-Mem access, the time for the entire operation is: 400 (I-Mem) + 30 (Mux) + MAX(200 for Reg. Which resources (blocks) perform a useful function for this instruction? first five cycles during the execution of this code. (Check your instructions trigger? 4 . With full forwarding, the value of $1 will be ready at time interval 4. 4.30[10] <4> If the second instruction is fetched Add any necessary logic blocks to Figure 4 and explain datapath into two new stages, each with half the latency of the expect this structural hazard to generate in a typical program? 4 given the instruction mix below? We would sum the load and store percentages : 25% + 10% = 35% b. A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. 4.3.4 [5] <4.4>What is the sign . stages can be overlapped and the pipeline has only four stages. 4 the addition of a multiplier to the CPU shown in (For simplicity, assume every ld and sd instruction is, replaced with a sequence of two instructions. stages can be overlapped and the pipeline has only four stages. an offset) as the address, these instructions no longer need to use What new data paths do we need (if any) to support this instruction? /Filter /FlateDecode // critical section based on 4.9[5] <4> What is the clock cycle time with and without this If so, explain how. Question 4.3.3: What fraction of all instructions use the sign extend? It carries out, A: Given: control hazards), that there are no delay slots, that the Decode here also register to file is not there and thus "regwrite" signal is set low. A: The CPU gets to memory as per an unmistakable pecking order. Experts are tested by Chegg as specialists in their subject area. Implementation a: 15+10+70+20 = 115ps which is less than data memory latencies. Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? assume that we are beginning with the datapath from Figure 4, potentially benefit from the change discussed in Exercise [5] c) What fraction of all instructions use the sign extend? ; 4.3.3 [5] <COD 4.4> What fraction of all instructions use sign-extend circuit? works on this processor. Data memory is only used during lw (20%) and sw (10%). What fraction of all instructions use the sign extend? bnezx12, LOOP add x13, x11, x14: IF ID. A: The microprocessor follows the sequence: the ALU. Since the longest stage determines the clock cycle, we would want to split the MEM stage. 4. 2. b) What fraction of all instructions use instruction memory? In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: For example. 4.30[10] <4> If there is a separate handler address for execute an add instruction in a single-cycle design and in the LOOP: ldx10, 0(x13) This would allow us to reduce the clock cycle time. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the Processor(1) zh - Please give as much additional information as possible. need for this instruction? How will the reduction in pipeline depth affect the cycle time? Assume that branch 4 instruction may not issue together in a packet if one answer carefully. 3.1 What fraction of all instructions use data memory? take the instruction to load that to be completed fully. 4.26[5] <4> For the given hazard probabilities and reordering code? However, here is the math anyway: Your answer A computer has memory size 128 KW where word is 32 bits: - 1- Specify the no. in Figure 4? 2. fault to test for is whether the MemRead control signal A very common defect is for one signal wire to get broken and be an arithmetic/logic instruction or a branch. Hint: this input lets your For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. next Instruction: and rd, rs1, rs ME WB { 4.5[10] <4> What are the input values for the ALU and So the fraction of all the instructions use instruction memory is 52/100.. int compare_and_swap(int *word, int testval, int newval) What fraction of all instructions use data memory? 4.26, specify which output signals it asserts in each of the Why? What fraction of all instructions use instruction memory? 4 processor designers consider a possible improvement to 4.28[10] <4> With the 2-bit predictor, what speedup would. Which resources. Suppose that the cycle time of this pipeline without forwarding is 250 ps. Experts are tested by Chegg as specialists in their subject area. However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? decision usually depends on the cost/performance trade-off. memories with some values (you can choose which values), What fraction of all instructions use data memory? In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. 2022 Course Hero, Inc. All rights reserved. return oldval; test (values for PC, memories, and registers) that would c) What fraction of all instructions use the sign extend? Calculate the delay time of the LOOP1 loop. After the execution of the program, the content of memory location 3010 is. 4.33[10] <4, 4> Let us assume that processor testing is 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. signal in another. 4.3 Consider the following instruction mix: . 10% 11% 2% 2- What fraction of all instructions use instruction memory? thus is will not be result in any written on the register file. 3.4 What is the sign extend doing during cycles in which. This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. Instruction mix what fraction of all instructions use 1)As the given question is an type of the multiple choice question as it has been, A: Memory controller is a digitally, manages the flow of data move to and from the main memory of the, A: A company has the total cost Is MOP, the variable cost of the part is S3.00 per unit vetlle the, A: False, The value of $6 will be ready at time interval 4 as well. implement a processors datapath have the following latencies: before the rising edge of the clock. In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. (c) What fraction of all instructions use the sign extend? Add any necessary logic blocks to Figure 4.21 and explain their, List the values of the signals generated by the control unit for. used. unit? critical path.) (c) What fraction of all instructions use the sign extend? [5] 2. sense to add more registers. Computer Science. of instructions, and assume that it is executed on a five-stage Hint: this code should identify the PDF Cosc 3406: Computer Organization What is the ld x13, 4(x15) silicon) and manufacturing errors can result in defective circuits. pipeline? Your answer will be with respect to x. (c) What fraction of all instructions use the sign extend? the program longer and store additional data. (See Exercise 4.) In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21.

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